Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

Rift2Core

License

LICENSE


Based on Chisel3, Rift2Core is a 9-stage, dual-issue, out-of-order, 64-bits RISC-V Core, which supports RV64GC and M, S, U mode.

RiftCore is the previous version of Rift2Core in Verilog.


How to Setup

  • Setup Repo
  • Setup sbt
  • Setup verilator and gtkwave
  • Compile chisel3 to verilog
  • Compile Model of Rif2Chip
  • Test a single ISA with waveform
  • Test all ISA without waveform

Rift To Go

Download Pre-compile FIRRTL Here:

Master Version Develop Version

Download Pre-compile Verilog Here:

Master Version Develop Version

API

API Here

Wiki

Wiki in Chinese

Wiki in English(Comming Soon!)

Sponsorships

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Micro-Architecture

FrontEnd

FrontEnd

BackEnd

BackEnd