Based on Chisel3, Rift2Core is a 9-stage, dual-issue, out-of-order, 64-bits RISC-V Core, which supports RV64GC and M, S, U mode.
RiftCore is the previous version of Rift2Core in Verilog.
- Setup Repo
- Setup sbt
- Setup verilator and gtkwave
- Compile chisel3 to verilog
- Compile Model of Rif2Chip
- Test a single ISA with waveform
- Test all ISA without waveform
Rift To Go
Download Pre-compile FIRRTL Here:
Download Pre-compile Verilog Here: