This project has been upstreamed to chipsalliance/chisel. Any proposed improvements to this repository should be redirected to pull requests on upstream Chisel.

This library provides a ChiselStage-like interface for compiling a Chisel circuit using the MLIR-based FIRRTL Compiler (MFC) included in the llvm/circt project. This is an alternative to the Scala-based FIRRTL Compiler (SFC) that Chisel uses by default and is developed in chipsalliance/firrtl.

The MFC is a feature complete FIRRTL compiler, but does not support every annotation and custom transform-backed extension to Chisel.

If you suspect a CIRCT bug or have questions, you can file an issue on this repository, post on Discourse, or file an issue on CIRCT.

Include the following in your build.sbt. See the badges above for latest release or snapshot version.

libraryDependencies += "com.sifive" %% "chisel-circt" % "X.Y.Z"

Additionally, install CIRCT. You can either:

1. Download a release from llvm/circt releases
2. Build and install from source

This project is compatible with (at least) the released version of CIRCT that it was tested with in CI. This is documented in the release notes of the latest tag.

After CIRCT installation is complete, you need firtool (the tool provided with CIRCT to compile FIRRTL circuits) on your path so chisel-circt can use it.

Alternatively, a base project is provided in sifive/chisel-circt-demo.

You can use circt.stage.ChiselStage almost exactly like chsel3.stage.ChiselStage. E.g., the following will compile a simple module using CIRCT.

import chisel3._

class Foo extends RawModule {
  val a = IO(Input(Bool()))
  val b = IO(Output(Bool()))

  b := ~a
}

/* Note: this is using circt.stage.ChiselStage */
val verilogString = circt.stage.ChiselStage.emitSystemVerilog(new Foo)

println(verilogString)
/** This will return:
  *
  * module Foo(
  *   input  a,
  *   output b);
  *
  *   assign b = ~a;
  * endmodule
  */

The method emitSystemVerilog also accepts parameters for Chisel arguments and Firtool options.

Another option is using emitSystemVerilogFile to generate output files. Eg. Below the files are created on "./generated" directory (passing Chisel args) and without debug source locators (firtool option).

ChiselStage.emitSystemVerilogFile(
  new Foo,
  Array("--target-dir", "generated"),
  Array("--strip-debug-info"),
)