- A language to describe digital hardware
- Compatible with EDA tools as it generate the corresponding VHDL/Verilog file
- Much more powerful than VHDL, Verilog and SystemVerilog by its syntaxes and features
- Much less verbose than VHDL, Verilog and SystemVerilog
- Not an HLS, nor based on the event driven paradigm
- Only generating what you asked him in a one to one way (no black-magic, no blackbox)
- Not introducing Area/Performance overhead in your design (versus a hand written VHDL/Verilog)
- Based on the RTL description paradigm, but can go much further
- Allowing you to use Object Oriented Programming and Functional Programming to elaborate your hardware and verify it
- Free and can be used in the industry without any license
- Presentation of the language
- SBT base project
- Google group
SBT (Scala build tool)
scalaVersion := "2.11.6" libraryDependencies ++= Seq( "com.github.spinalhdl" % "spinalhdl-core_2.11" % "latest.release", "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "latest.release" )
You can force to pick a specific SpinalHDL version by replacing the 'latest.release'. See https://github.com/SpinalHDL/SpinalTemplateSbt/blob/master/build.sbt
The SpinalHDL core is using the LGPL3 license while SpinalHDL lib is using the MIT one. That's for the formalities. But there is some practices statements of those license implications :
Your freedoms are :
- You can use SpinalHDL core and lib in your closed/commercial projects.
- The generated RTL is yours (.vhd/.v files)
- Your hardware description is yours (.scala files)
Your obligations (and my wish) are :
- If you modify the SpinalHDL core (the compiler itself), please, share your improvements.
Also, SpinalHDL is provided "as is", without warranty of any kind.